Four-channel Scalable Radio Digital Receiver System

In response to the requirements of high sampling rate, wide bandwidth, multi-channel amplitude-phase consistency, as well as high-speed direct sampling and time-domain data storage in current radio observation devices, this paper investigates and analyzes the technical architecture and functionalities of digital processing systems in multiple radio observation devices. It proposes a 4-channel digital receiver system based on ZYNQ SOC and core components such as ADS54J60. This system achieves a maximum sampling rate of 1GSPS per single channel, demonstrating flexibility and scalability, which allows for the addition of expansion cards to increase sampling channels for meeting the fundamental requirements of future large-scale expandable radio interference arrays. The system consists of three parts: a high-speed data acquisition card, an optical communication receiving card, and a server. Currently, the high-speed serial interface technology based on SerDes has achieved direct sampling with a quantization accuracy of 16 bits and a sampling rate of 300 MSPS, providing a full-scale signal-to-noise ratio of 60 dB, a 40 Gbps SFP+ data transmission bandwidth, and a 1.5 GB/s PCIe communication bandwidth. It can capture analog signals in the intermediate frequency range of 4.5 MHz to 150 MHz. The system has completed both hardware and software design and testing. In our tests, we sampled a 10 MHz sine wave signal with an amplitude of 125 mV, and the amplitude difference between the 4 channels was less than 1 mV, with a phase delay of less than 3.3 ns. The system integrates programmable SFP+ communication interfaces and a multi-machine synchronization mechanism to accommodate the synchronous acquisition needs of multi-element arrays. It can also store the data of the original radio signals, providing more detailed time-domain data for radio research.