Unconventional Use of SRAM in a 32-bit SOPC System

For reducing the level of noise coming from a digital sub-system in a high-speed low-noise digital-analog hybrid system while ensuring the reliability of the system with the allocation of limited resources in an FPGA, a 16-bit SRAM can be used in a 32-bit embedded SOPC system. However, it is necessary for users to create a new component for the 16-bit SRAM since there is no such an unusual component in a 32-bit SOPC framework built in the Quartus II IDE. According to the Avalon bus specification, we present a method to build the 16-bit SRAM component via the Verilog HDL programming. We first briefly introduce the structure of the SOPC and its interfaces in our FPGA board. We then describe the design techniques for the 16-bit SRAM component, including the determination of rules of reading, writing, chip selecting, and bit-width parametric processing of data. We give the details about the procedure of creating the component in the Quartus II IDE, including definitions of the SRAM signal associated interfaces, and corresponding timing setup. The Verilog program is listed and the method for determining values of the read and write timing parameters related to a specific SRAM is illustrated. The component has been implemented and used in a Quartus project for an astronomical EMCCD camera. We present the measurements of some waveforms generated by an EMCCD timing generator in our FPGA. These waveforms are consistent with our simulations, indicating that the 16-bit SRAM component and the entire system are working properly. We also discuss some possible applications of the 16-bit SRAM component.