A Design of an Improved High-Speed FIR Digital Filter Based on the FPGA

With steady theoretical and technological development of digital signal processing, digital devices are rapidly replacing some analog devices due to their portability and highly reliable designs/implementations. In radio astronomy digital-processing techniques have been increasingly applied in receivers, and have become important parts of receivers. The design of an FIR digital filter is critical in implementing digital techniques. In digital-processing modules for signals in radio-astronomy observation Analog-to-Digital Converters of operating frequencies at a few GHz are usually used. At so high frequencies high-rate data flows can form bottlenecks in data-storage processes. To avoid bottlenecks the hardware design of a digital filter needs to limit the data speed or to create diversions of data flows. The operating speed of a conventional filter is too slow though. Distributed Arithmetic (DA) algorithms have been proposed to improve speeds of conventional filters, but it is very difficult to achieve the optimal balance between the operating speed and the required resource of logic units in a conventional filter. As a result a conventional filter generally takes a large fraction of the chip area and uses a large amount of logic units. An FIR filter based on the Reduced Adder Graph algorithm can reduce the needed resources of logic units, but is slower than an improved DA filter. The issue of achieving a balance between data-rate performance and hardware-resource requirement becomes increasingly important and yet also increasingly difficult in designing high-speed FIR digital filters, as filters tend to have more taps. In this paper we present a new design of a parallel FIR digital filter by using the basic theory of high-speed parallel FIR digital filters, the bit-plane construction method, the CSD coding technique, and a signal-extraction algorithm. After having been simulated in the Matlab, the design was complied, simulated, and synthesized in the Quartus II; it was finally loaded into an FPGA device for test measurements. Our simulation and test results demonstrate the capability of our design in solving issues of achieving balances between the filter order, data-flow rate, and requirement of hardware resources. In practice, such balances can be realized using settings tailored to specific requirements on filter performance. In conclusion, our design of an improved high-speed FIR digital filter provides a new idea for designing digital filters to be used in radio telescopes.